Pre-request: Verilog & VLSI System Design
Lecturer: Alan P. Su, Ph.D., alansuphd@mail.ncku.edu.tw
No textbook required. Lecture notes offered in class
References
- C++, http://www.cplusplus.com/doc/tutorial/
- IEEE 1666-2010, Download free from http://standards.ieee.org/getieee/1666/download/1666-2011.pdf
- SystemC: From the Ground Up, Black & Donovan, Kluwer Academic, May 2004, ISBN 1402079885
Hours: Every Tuesday 18:10~21:00, maximum capacity: 25 (I hope)
Abstract
We will start with a general introduction to Electronic System Level design methodology (ESL). In this section students should have the awareness why ESL is needed in today's system designs, what ESL can do and its fundamental methodology. And then we move into the learning of SystemC, the industry standard language to ESL modeling. We will go through the language step by step and thru and thru. Students do not need to have prior knowledge in C/C++ programming. Students will be trained how to design hardware components in SystemC and learn differences between synthesis and simulation subsets. An industrial grade High-Level Synthesis (HLS) tool will be employed to facilitate the training. In second half of the course students are required to use HLS to design and synthesize HW components given in assignments. Components developed in assignments are expected to work not only at behavior level but also at RTL codes directly synthesized out of behavior codes.
After the training students should be familiar with:
1. ESL general concepts
2. C/C++
3. SystemC
4. Behavior Coding
5. High-Level Synthesis
Agenda
Weeks 1: Brief Introduction to ESL
Weeks 2~6: C Overview
Weeks 7~9: C++ Overview
Midterm 1 in Week 10
Weeks 11~15 SystemC
Weeks 16~17: Behavior Coding in SystemC
Week 18: SystemC & System Modeling
Final Exam in Week 19
Assignments
8 Programming assignments
Score System
Programming Assignments 40%
Midterms 30%
Final 30%
- 教師: 蘇培陞